The r2 hardware arrived Friday. Had CPLD images flashed by Saturday. I'm crazy-busy writing enough firmware for the ESP32 to test it. Until then, photos...
Dorsal surface on the left, ventral on the right.
US quarter in the foreground for scale.
Digit3 and MC connected
This shot through the microscope shows the proximal half of the CPLD, secure element, LED, and our logo.
Board mated to my test harness, which has the same footprint. This is the spatial relationship the board will have with the host CPU PCB. All the clearances pass.
