This will eventually become part of the user's manual, or be put in a documentation folder someplace. But for now, you can see it on the blog. :-)

The identities of the pins in the header are fixed, and will not change prior to release.

Update 2015.10.25: Assembly complete

These four PCBs are the front and back of the two debug boards. The smaller boards are just pass-through adapters for the digit connectors so that we can tap signals on the digits, isolate any potential electrical abnormalities, and so-forth. There is probably no reason anyone but us would need them.

If you are the sort to roll your own, I've shared the PCB via OshPark. The 40-pin mezzanine connector is easy to solder on with paste and a hotplate.

Update 2015.09.15

We have our debug harness designed and rolled. It will be arriving in the next several days. It should be re-stated that this board is not required for anyone (even most developers). Firmware upload happens over USB.

For those who want to design add-on hardware or do deep firmware-debugging work, this harness will be offered for sale on our site at cost.

Serious hardware engineers can also drop us a line, and we will provide the KiCAD files required to make the PCB. These can be used as a template for custom add-on boards.


This is the pinout for the expansion header

The 40-pin expansion header can be found on the dorsal surface of the main PCB. It looks like this:

The pin orientations given above can be matched with the table below:

|        fxn |  Class | Pin | Pin | Class | fxn         |
|------------|--------|-----|-----|-------|-------------|
|     ~RESET | SYSTEM |  1  |  40 | CPLD  | CPLD_OE     |
|   CPLD_TMS |  CPLD  |  2  |  39 | CPLD  | ~CPLD_RESET |
|   CPLD_TCK |  CPLD  |  3  |  38 | ISP   | ~JTRST      |
|     BOOT_0 | SYSTEM |  4  |  37 | ISP   | JTCLK       |
|   CPLD_TDO |  CPLD  |  5  |  36 | ISP   | JTMS-SWDIO  |
|   CPLD_TDI |  CPLD  |  6  |  35 | USER  | ~EXP_RESET  |
|   UART3_RX |  USER  |  7  |  34 | USER  | IRQ_2       |
|   UART3_TX |  USER  |  8  |  33 | USER  | IRQ_1       |
|   ~FSMC_E1 |  USER  |  9  |  32 | USER  | IRQ_0       |
|   ~FSMC_WE |  USER  | 10  |  31 | I2C   | SDA         |
|    FSMC_D0 |  USER  | 11  |  30 | I2C   | SCL         |
|    FSMC_D1 |  USER  | 12  |  29 | USER  | ~FSMC_OE    |
|    FSMC_D2 |  USER  | 13  |  28 | Power | Vbatt       |
|    FSMC_D3 |  USER  | 14  |  27 | Power | Vbatt       |
|    FSMC_D4 |  USER  | 15  |  26 | Power | 3.3v        |
|    FSMC_D5 |  USER  | 16  |  25 | Power | 3.3v        |
|    FSMC_D6 |  USER  | 17  |  24 | Power | GND         |
|    FSMC_D7 |  USER  | 18  |  23 | Power | GND         |
|   FSMC_A16 |  USER  | 19  |  22 | Power | GND         |
|   FSMC_A17 |  USER  | 20  |  21 | Power | GND         |
Notes:

The ISP, SYSTEM, and CPLD pin classes are meant to be used during system programming. They should only be used by developers.

The 3.3v regulator on the glove has enough headroom to supply an expansion board with ~150mA without causing drop-outs. If your application requires more current than this, the Vbatt line will let you draw from the battery directly. The draw will still be registered by the on-board PMIC circuitry, so your application can monitor current-draw accurately.

The I2C pins are available for add-ons and user expansion, but the bus is shared with the other i2c peripherals in the glove. So they are not available for user remap.

All USER pins are uncommitted, and their labeled functions correspond to their suggested purpose. If a given expansion idea doesn't need an 8-bit memory-mapped i/o port, the FSMC pins can be re-assigned to timers, analog-to-digital conversion, additional serial buses, etc.

A full alternate-option table can be obtained by inquiry to ian@manuvr.io.